English: This session focuses on state-of-the-art research on advanced clock generation and distribution circuits, including oscillators, frequency synthesizers, and low-jitter clock distribution networks, etc., for modern SoC, communication, and high-speed interface systems. Original contributions on theoretical advances, innovative circuit designs, and experimental validations are welcome. This session targets key performance improvements covering ultra-low phase noise and jitter, fast frequency hopping, high spurious suppression, low power consumption, compact integration, and robust PVT stability, offering a platform to share cutting-edge progress in clocking circuit techniques.
中文: 本专题聚焦先进时钟产生与分配电路的前沿研究,涵盖振荡器、频率综合器与低抖动时钟分配网络等,面向现代 SoC、通信及高速接口系统。欢迎理论突破、创新电路设计与实验验证方面的原创性投稿。本专题旨在提升超低相位噪声与抖动、快速跳频、高杂散抑制、低功耗、紧凑集成与鲁棒 PVT 稳定性等关键性能,为分享时钟电路技术的前沿进展提供交流平台。