Track 25: Integrated Circuit Security and Reliability Verification

English: Verification of chip-design security and reliability is a major technical challenge jointly faced by academia and industry as integrated circuits enter the nanometer era. This forum focuses on the frontier direction of "Integrated Circuit Security and Reliability Verification," centering on core topics such as processor security, hardware Trojan detection, and side-channel analysis, to deeply explore the severe security challenges faced by chips; at the same time, it discusses how to leverage formal methods and artificial intelligence techniques to break through the efficiency bottlenecks of EDA tools in the design, verification, and testing stages, and to explore more effective defense strategies.

中文: 芯片设计安全与可靠性的验证，是集成电路进入纳米时代后学术界与工业界共同面临的重大技术挑战。本论坛聚焦于"集成电路安全及可靠性验证"这一前沿方向，围绕处理器安全、硬件木马检测、侧信道分析等核心议题，深入探讨芯片面临的严峻安全挑战；同时，讨论如何利用形式化方法与人工智能技术，突破EDA工具在设计、验证与测试等环节的效率瓶颈，并探索更为有效的防御策略。