Working Time: 9:30-18:00
2026 The 11th International Conference on Integrated Circuits and Microsystems
    Email: icicm_conf@vip.163.com
    Secretary: Ms. Mila Xiao(肖老师)

Track 2: RISC-V Open Architecture and Processor Chip Design

Track 2: RISC-V 开放架构与处理器芯片设计

Organizers / 组织者

Organizer / 组织者
Zihao Yu 余子濠
Senior Engineer, Institute of Computing Technology, Chinese Academy of Sciences
中国科学院计算技术研究所,高级工程师
Organizer / 组织者
Junyong Deng 邓军勇
Professor, Xi'an University of Posts and Telecommunications
西安邮电大学,教授

Abstract / 论坛简介

With the maturity of the RISC-V ecosystem, processor design is transitioning from traditional closed models to open collaboration. This forum, themed "RISC-V Open Architecture and Processor Chip Design," focuses on the open instruction set architecture RISC-V and its associated processor design methodologies. It aims to explore hot topics such as RISC-V open architecture, agile design methodologies, and processor chip design and verification flows.

随着RISC-V生态日趋成熟,处理器设计正从传统封闭模式向开放协作转型。本论坛以“RISC-V开放架构与处理器芯片设计”为主题,聚焦开放指令集架构RISC-V及其带来的处理器芯片设计方法,旨在探讨RISC-V开放架构、敏捷设计方法、处理器芯片设计与验证流程等热点问题。

Topics / 讨论主题

RISC-V and Custom Instructions / RISC-V和自定义指令
Processor Architecture Design and Simulators / 处理器架构设计和模拟器
Processor Functional Verification and Performance Evaluation / 处理器功能验证和性能评测方法
Processor PPA Front-end Optimization / 处理器PPA前端优化方法
EDA Tools and Back-end Physical Design Optimization / EDA工具和芯片后端物理设计优化
Processor Chip Design Platforms / 处理器芯片设计平台

Invited Speakers / 拟邀请报告人

Invited Speaker (Pending) / 拟邀请报告人
Biwei Xie 解壁伟
Institute of Computing Technology, Chinese Academy of Sciences
中国科学院计算技术研究所
Invited Speaker (Pending) / 拟邀请报告人
Xiaoke Su 苏小可
Institute of Computing Technology, Chinese Academy of Sciences
中国科学院计算技术研究所
Invited Speaker (Pending) / 拟邀请报告人
Zhipeng Huang 黄志鹏
Beijing Institute of Open Source Chip
北京开源芯片研究院